The present invention relates to a logic gate partitioning system for the logic design of a high-speed logic operation apparatus, and more particularly to an automatic logic gate partitioning system suitable for a hierarchically described logic structure.
Partitioning of logic gates is the process of assigning a multiplicity of logic gates to be connected for execution of a desired logic operation to hardware components such as, for example, boards, modules or LSI chips while satisfying restrictive conditions such as the maximum allowable number of logic gates which a hardware component can accommodate and the maximum allowable number of pins which the hardware component can carry. Heretofore, various methods of automatically performing the partitioning of logic gates by using a computer have been proposed.
General methods of automatically assigning logic gates pay attention to connection information between logic gates in partitioning the logic gates. One known method is a logic gate assigning method in which some cores are first produced and logic gates are incorporated into the cores in a descending order of the number of signal connection lines up to an allowable number of logic gates the hardware component can accommodate (e.g., see I. Nishioka et. al.: An approach to Gate Assignment and Module Placement for Printed Wiring Boards, IEEE Trans. Comput., Vol. C-29, No. 8, pp. 681-688 (1980)). A mapping method is also known in which logic gates are partitioned into some functional groups on the basis of connection information to assign the logic gates to a mounting unit for each functional group (e.g., see R. L. Russo: A Heuristic Procedure for the Partitioning and Mapping of Computer, Vol. C-20, No. 12, pp. 1455-1462 (1971)). Further, a method in which hierarchical logic information is utilized when a circuit is partitioned functionally (e.g., see T. S. Payne et. al.: Automated Partitioning of Hierarchical Specified Digital Systems. Proc. 19th Design Automation Conf., pp. 182-192 (1982)) has been published. However, all of those methods perform the partitioning of logic gates by treating all of the logic gates.
When the logic design of a high-speed logic operation apparatus such as a large computer including a multiplicity of logic gates is made, data corresponding to one million logic gates will have to be handled. A conventional automatic logic gate partitioning method which directly handles or treats logic gates needs examination of connection relations among one million logic gates, with a result that the logic gate partitioning procedure in the logic design of the computer is time-consuming and is not practical.